The semiconductor industry has experienced rapid growth due to continuous improvements in the integration density of a variety of electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). For the most part, this improvement in integration density has come from repeated reductions in minimum feature size (e.g., shrinking the semiconductor process node towards the sub-20 nm node), which allows more components to be integrated into a given area. As the demand for miniaturization, higher speed and greater bandwidth, as well as for lower power consumption and latency, has grown recently, there has grown a need for smaller and more creative techniques for forming semiconductor structures.
As semiconductor technologies further advance, stacked semiconductor devices, e.g., 3D integrated circuits (3DIC), have emerged as an effective alternative to further reduce the physical size of a semiconductor device. In a stacked semiconductor device, active circuits such as logic, memory, processor circuits, and the like are fabricated on different semiconductor wafers. Two or more semiconductor wafers may be installed on top of one another to further reduce the form factor of the semiconductor device. The stacked semiconductor devices may provide a higher density with smaller form factors and allow for increased performance and lower power consumption. Further, by stacking semiconductor devices, circuits can be formed on one semiconductor wafer by processes that are incompatible with circuits formed and/or processes performed on another semiconductor wafer, and vice versa.